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asynchronous sram 256k x 16 sram +3.3v supply revolutionary pinout gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. galvantech, inc. reserves the right to chang e products or specifications without notice . rev. 7/9 9 galvantech, inc. 3080 oakmead village drive, santa clara, ca 9505 1 tel (408) 566-0688 fax (408) 566-069 9 web site http://www.galvantech.co m feature s ? fast access times: 10, 12, and 15n s ? fast oe# access times: 5, 6, and 7n s ? single +3.3v + 0.3v power suppl y ? fully static -- no clock or timing strobes necessar y ? all inputs and outputs are ttl-compatibl e ? three state output s ? center power and ground pins for greater noise immunit y ? easy memory expansion with ce# and oe# option s ? automatic ce# power dow n ? high-performance, low-power consumption, cmos double-poly, double-metal proces s ? packaged in 44-pin, 400-mil soj and 44-pin, 400-mil tso p option s markin g ? timin g 10ns access -10 12ns access -12 15ns access -15 ? package s 44-pin soj (400 mil) j 44-pin tsop (400 mil) t s ? power consumptio n standard non e low l ? temperatur e commercial none ( 0 c to 70c) industrial i ( -40 c to 85c ) general descriptio n the gvt73256a16 is organized as a 262,144 x 16 sram using a four-transistor memory cell with a high performance, silicon gate, low-power cmos process. galvantech srams are fabricated using double-layer polysilicon, double-layer metal technology . this device offers center power and ground pins for improved performance and noise immunity. static design eliminates the need for external clocks or timing strobes. for increased system flexibility and eliminating bus contention problems, this device offers chip enable (ce#), separate byte enable controls (ble# and bhe#) and output enable (oe#) with this organization . the device offers a low power standby mode when chip is not selected. this allows system designers to meet low standby power requirements . 1 2 3 4 5 6 7 8 9 10 32 31 30 29 28 27 26 25 24 23 19 20 21 11 12 13 14 15 16 22 18 17 a16 a15 dq12 dq11 nc a14 a13 a12 a11 oe# bhe# dq16 dq15 vss vcc a2 a3 dq3 dq4 we# a5 a6 a7 a8 a4 ce# dq1 dq2 vcc vss a17 a1 pin assignment 44-pin soj 44-pin tsop 33 34 35 36 a0 a9 a10 ble# 41 42 43 44 37 38 39 40 dq7 dq8 dq5 dq6 dq10 dq9 dq14 dq13
july 22, 199 9 2 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. functional block diagra m ce# address buffer row decoder column decoder memory array 512 rows x 512 x 16 columns i/o control we# oe# dq8 dq1 power down a17 a0 dq16 dq9 bhe# ble# vcc vss
july 22, 199 9 3 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. truth table pin description s mod e ce # we # oe # ble # bhe # dq1- dq 8 dq9- dq1 6 powe r low byte read (dq1-dq8 ) l h l l h q high- z activ e high byte read (dq9-dq16 ) l h l h l high- z q activ e word read (dq1-dq16 ) l h l l l q q activ e low byte write (dq1-dq8 ) l l x l h d high- z activ e high byte write (dq9-dq16 ) l l x h l high- z d activ e word write (dq1-dq16 ) l l x l l d d activ e output disabl e l x x h h high- z high- z activ e l h h x x high- z high- z activ e standb y h x x x x high- z high- z standb y soj & tsop pin number s symbo l typ e descriptio n 1, 2, 3, 4, 5, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 42, 43, 4 4 a0-a1 7 inpu t addresses inputs: these inputs determine which cell is addressed . 1 7 we # inpu t write enable: this input determines if the cycle is a read or write cycle. we# is low for a write cycle and high for a read cycle . 6 ce # inpu t chip enable: this active low input is used to enable the device. when ce# is low, the chip is selected. when ce# is high, the chip is disabled and automatically goes into standby power mode . 39, 4 0 ble#, bhe # inpu t byte enable: these active low inputs allow individual bytes to be written or read. when ble# is low, the data is written to or read from the lower byte (dq1-dq8). when bhe# is low, the data is written to or read from the higher byte (dq9-dq16) . 4 1 oe # inpu t output enable: this active low input enables the output drivers . 7, 8, 9, 10, 13, 14, 15, 16, 29, 30, 31, 32, 35, 36, 37, 3 8 dq1-dq1 6 input/outpu t sram data i/o: data inputs and data outputs. lower byte is dq1-dq8 and upper byte is dq9-dq16 . 11, 3 3 vc c suppl y power supply: 3.3v + 0.3v % 12, 3 4 vs s suppl y groun d
absolute maximum ratings * voltage on vcc supply relative to vss........-0.5v to +4.6 v v in ..........................................................-0.5v to vcc+0.5 v storage temperature (plastic) ..........................-5 5 o c to +12 5 o junction temperature .....................................................+12 5 o power dissipation ...........................................................1.0 w short circuit output current .......................................50m a *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . july 22, 199 9 4 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. dc electrical characteristics and recommended operating condition s (all temperature ranges; vcc = 3.3v + 0.3v unless otherwise noted ) capacitanc e descriptio n condition s symbo l mi n ma x unit s note s input high (logic 1) voltag e v i h 2. 2 vcc+0. 5 v 1, 2 input low (logic 0) voltag e v i l -0. 5 0. 8 v 1, 2 input leakage curren t 0v < v i n < vc c i l i - 5 5 u a output leakage curren t output(s) disabled, 0 v < v ou t < vc c i l o - 5 5 u a output high voltag e i o h = -4.0m a v o h 2. 4 v 1 output low voltag e i o l = 8.0m a v o l 0. 4 v 1 supply voltag e vc c 3. 0 3. 6 v 1 descriptio n condition s sy m ty p powe r -1 0 -1 2 -1 5 unit s note s power supply current: operatin g device selected; ce# < v i l ; vcc =max; f= f ma x ; outputs ope n ic c 9 0 standar d 24 0 21 0 17 5 m a 3, 1 4 lo w 24 0 21 0 17 5 ttl standb y ce# > v i h ; vcc = max; f= f ma x i sb 1 2 5 standar d 7 0 6 0 5 0 m a 1 4 lo w 7 0 6 0 5 0 cmos standb y ce1# > vcc -0. 2 ; vcc = max ; all other inputs < vss +0.2 or > vcc -0.2; all inputs static; f= 0 i sb 2 0. 1 standar d 1 0 1 0 1 0 m a 1 4 lo w 3. 0 3. 0 3. 0 descriptio n condition s symbo l ma x unit s note s input capacitanc e t a = 2 5 o c; f = 1 mh z vcc = 3.3 v c i 6 p f 4 input/output capacitance (dq ) c i/ o 8 p f 4
july 22, 199 9 5 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. ac electrical characteristics (note 5) (all temperature ranges; vcc = 3.3 v + 0.3v ) descriptio n - 1 0 - 1 2 - 1 5 sy m mi n ma x mi n ma x mi n ma x unit s note s read cycl e read cycle tim e t r c 1 0 1 2 1 5 n s address access tim e t a a 1 0 1 2 1 5 n s chip enable access tim e t ac e 1 0 1 2 1 5 n s output hold from address chang e t o h 3 3 3 n s chip enable to output in low- z t lzc e 3 3 3 n s 4, 7 chip disable to output in high- z t hzc e 5 6 7 n s 4, 6, 7 output enable access tim e t ao e 5 6 7 n s output enable to output in low- z t lzo e 0 0 0 n s output enable to output in high- z t h z o e 5 6 7 n s 4, 6 byte enable access tim e t ab e 5 6 7 n s byte enable to output in low- z t lzb e 0 0 0 n s 4, 7 byte disable to output in high- z t hzb e 5 6 7 n s 4, 6, 7 chip enable to power-up tim e t p u 0 0 0 n s 4 chip disable to power-down tim e t p d 1 0 1 2 1 5 n s 4 write cycl e write cycle tim e t w c 1 0 1 2 1 5 n s chip enable to end of writ e t c w 8 8 9 n s address valid to end of write, with oe# hig h t a w 8 8 9 n s address setup tim e t a s 0 0 0 n s address hold from end of writ e t a h 0 0 0 n s write pulse widt h t wp 2 1 0 1 0 1 1 n s write pulse width, with oe# hig h t wp 1 8 8 9 n s data setup tim e t d s 5 6 7 n s data hold tim e t d h 0 0 0 n s write disable to output in low- z t lzw e 3 4 5 n s 4, 7 write enable to output in high- z t hzw e 5 6 7 n s 4, 6, 7 byte enable to end of writ e t b w 8 8 9 n s
ac test condition s input pulse level s 0v to 3.0v input rise and fall time s 1.5ns input timing reference level s 1.5v output reference level s 1.5v output loa d see figures 1 and 2 output load s vt = 1.5v 30 pf dq z 0 = 50 w fig. 1 output load equivalent 50 w dq 3.3v 317 w 351 w fig. 2 output load equivalent 5 pf july 22, 199 9 6 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. note s 1. all voltages referenced to vss (gnd) . 2. overshoot: v i h +6.0v for t t rc /2 . undershoot: v i l -2.0v for t t rc / 2 3. i c c is given with no output current. i c c increases with greater output loading and faster cycle times . 4. this parameter is sampled . 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted . 6. output loading is specified with c l =5pf as in fig. 2. transition is measured + 500mv from steady state voltage . 7. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe . 8. we# is high for read cycle . 9. device is continuously selected. chip enable and output enables are held in their active state . 10. address valid prior to, or coincident with, latest occurring chip enable . 11. t r c = read cycle time . 12. chip enable and write enable can initiate and terminate a write cycle . 13. capacitance derating applies to capacitance different from the load capacitance shown in fig. 1. 14. typical values are measured at 3.3v, 2 5 o c and 20ns cycle time . data retention electrical characteristics (l version only ) descriptio n condition s symbo l mi n ty p ma x unit s note s vcc for retention dat a v d r 2 v data retention curren t ce# > vcc -0. 2 ; all other inputs < vss +0.2 or > vcc -0.2; all inputs static; f= 0 vcc = 2 v i ccd r 0. 2 1. 6 m a 1 3 vcc = 3 v i ccd r 0. 3 2. 4 m a 1 3 chip deselect to data retention tim e t cd r 0 n s 4 operation recovery tim e t r t r c n s 4, 1 1
july 22, 199 9 7 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. low vcc data retention wavefor m read cycle no. 1 (8, 9 ) read cycle no. 2 (7, 8, 10, 12 ) v cc ce# data retention mode v dr 3.0v 3.0v v ih v il t rc t cdr addr valid t rc data valid t oh t aa previous data valid q ce# t rc data valid t lzce t ace oe# high z t aoe t lzoe t hzce t hzoe ble# bhe# q undefined don't care t hzbe t lzbe t abe
july 22, 199 9 8 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. write cycle no. 1 (7, 12, 13 ) (write enable controlled with output enable oe# active low) ) write cycle no. 2 (12, 13 ) (write enable controlled with output enable oe# inactive high ) addr t wc t ah t ds data valid ce# we# d q t dh t wp2 t as t aw t cw high z t hzwe t lzwe ble# bhe# t bw addr t wc t ah t ds data valid high z ce# we# d q t dh t wp1 t as t aw t cw undefined don't care ble# bhe# t bw
july 22, 199 9 9 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. write cycle no. 3 (12, 13 ) (chip enable controlled ) write cycle no. 4 (12, 13 ) (byte enable controlled ) addr t wc t ah t ds don't care data valid ce# we# d q t dh t wp1 t aw t cw high z ble# bhe# t bw t as addr t wc t ah t ds don't care data valid ce# we# d q t dh t wp1 t aw t bw high z ble# bhe# t cw t as
july 22, 199 9 1 0 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. package dimension s note: all dimensions in inches (millimeters) 1.129 (28.68) 1.123 (28.52) .405 (10.29) .395 (10.03) pin #1 index .050 (1.27) typ .020 (0.51) .015 (0.38) max min or typical, min where noted. seating plane .380 (9.65) .360 (9.14) .095 (2.41) .080 (2.03) .148 (3.76) .138 (3.51) .030 (0.76) min .445 (11.30) .435 (11.05) 44-pin 400 mil plastic soj (j) note: all dimensions in inches (millimeters) .741 (18.81) .721 (18.31) .402 (10.21) .398 (10.11) pin #1 index .0315 (0.80) typ .018 (0.45) .010 (0.25) max min or typical, max where noted. seating plane .008 (0.20) .002 (0.05) .007 (0.18) .005 (0.12) .467 (11.86) .459 (11.66) 44-pin 400 mil plastic tsop (ts) .047 (1.20) max .032 (0.80) .024 (0.60) .016 (0.40)
july 22, 199 9 1 1 galvantech, inc. reserves the right to change products or specifications without notice . rev. 7/9 9 gvt73256a16 revolutionary pinout 256k x 16 galvantec h , inc. ordering informatio n gv t 73256a1 6 x x - x x x x galvantech prefi x part numbe r package (j = 400 mil soj, 15 = 15ns) speed ( 10 = 10ns, 12 = 12ns ts = tsop type ii) temperature (blank = commercial i = industrial) power (blank= standard, l= low power)

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